1. Field of the Invention
This invention relates to an integrated circuit and, more particularly to a phase-locked loop ("PLL") which can, within the feedback loop of the PLL, automatically detect and incrementally or directly lock upon a change in frequency of an input signal without substantially changing the PLL output signal frequency.
2. Description of the Related Art
A PLL is generally used in many areas of electronics to control the frequency and/or phase of a signal. Instances of use include, for example, applications as frequency synthesizers, analog-to-digital modulators, and clock recovery circuits.
As a clock recovery circuit, a PLL extracts a timing reference from, for example, an incoming data stream. The timing reference, or recovered clock, is typically synchronized to transitions of data within the data stream. The timing reference is output from the PLL arranged at the receiving end of, for example, a transmission channel. Using a PLL at the receiving end to reconstruct a clocking signal avoids having to forward with the data a separate clocking signal.
It is often desirable to modify the transition rate, or frequency, of the data stream forwarded across a transmission channel. Thus, a PLL at the receive end of the transmission channel must be capable of accepting an input signal at a variety of frequencies. If the input signal comprises data, it is important that the PLL support both regular and high-speed data rates. If the input signal is a clocking signal, the PLL must therefore accept and be able to choose among a variety of clocking frequencies.
While the input signal frequency to the PLL can vary depending on the transmission rate of the transmission mechanism (i.e., transmitter, receiver and channel) it is generally desired that a digital circuit coupled to the PLL output run at a relatively fixed rate. In most instances, the clocking frequency of the digital circuit or digital processor must run at a frequency within the manufacturer specified frequency range. Thus, when the PLL is locked upon the input signal frequency, the output signal (hereinafter "clocking signal") from the PLL must not exceed (or be less than) the operating specification of the digital circuit or digital processor. If the input signal frequency should change given, for example, an increase in data rate, the PLL will attempt to lock upon the changed input signal frequency.
In most cases, a PILL is used in applications where the clocking signal frequency output from the PLL must be a multiple of the input signal frequency. This arises since, in most instances, the digital processor can operate at a higher frequency than the transmitted data stream. To achieve a static discrepancy between the input signal and clocking signal frequencies, a clock divider is situated in the feedback loop of the PLL. The clock divider comprises a frequency division factor. An increase in the division factor will proportionally increase the clocking signal frequency relative to the input signal frequency. Thus, for example, if the input signal frequency is at 1.0.times. and division factor is 16, then the clocking signal frequency is 16.0.times..
An unfortunate aspect of the division factor is that it is typically static with changes in the input signal frequency. The inability to automatically or dynamically change commensurate with changes in the input signal frequency causes numerous problems with respect to the clocking signal. A static (or fixed) division factor presents a feedback signal frequency that will be momentarily dissimilar from an increasing input signal frequency during instances of "unlock". This will cause an increase in DC voltage to the PLL voltage controlled oscillator ("VCO"), resulting in an increase in the clocking signal frequency. Once the clocking signal achieves a steady state value, and the clocking signal is divided in the PLL feedback loop to substantially match the input signal frequency, then the PLL is said to be "locked". Unfortunately, when locked, the clocking signal may exceed the maximum frequency of the digital processor to which the clocking signal is connected. If this should occur, then the digital processor may lose its internal state and/or malfunction. Furthermore, if the clocking signal exceeds the maximum frequency of the digital processor, the VCO may be forced outside its dynamic operating range.